Defects (e.g., residual extra material) can cause electrically measurable faults (killer defects), depending on the chip layout as well as the layer and location of the defects. These faults are responsible for manufacturing-related malfunction of affected chips. So, a layer and fault sensitive defect density is important for yield enhancement and to control quality of process steps and product chips. See Staper, C. H., Rosner, R. J., Integrated Circuit Yield Management and Yield Analysis: Development and Implementation IEEE Transactions on Semiconductor Manufacturing, pp. 95-102, Vol. 8, No. 2, 1995, which is incorporated by reference herein in its entirety. Also see Ipri, A. C., Sarace, J. C. Integrated Circuit Process and Design Rule Evaluation Techniques RCA Review, pp. 323-350, Volume 38, Number 3, September 1977, and Buehler, M. G. Microelectronic Test Chips for VLSI Electronics VLSI Electronics Microstructure Science, pp. 529-576, Vol 9, Chap.9, Academic Press, 1983, both of which are incorporated by reference herein in their entireties. Electrical test structures are used to detect faults and to identify and localize defects.
Topography-related defects are particularly significant in the copper Damascene manufacturing method. In this manufacturing method, trenches and holes are etched in oxide layers, barrier films (e.g., Ta or TaN) and Cu films are deposited to fill the trenches, and chemical mechanical polishing (CMP) is used to remove the Cu overburden. It has been found that the deposition rate and CMP removal rates can have strong, pattern-dependent variations. These variations result in non-uniform layer thicknesses (i.e., topography) within the final patterns of each chip as well as chip-to-chip across wafers and lots. Since most chips have several layers of Cu metallization or other metallization, these thickness variations can further accumulate in each successive layer of processing resulting in complex overall topographical variations. “Extra material” defects are formed when residual material (e.g., Ta barrier metal) remains after any polishing step (i.e., “underpolish”). The usual countermeasure in this situation is to increase the CMP removal rate to achieve sufficient “overpolish.” However, too much overpolish can actually remove too much of the Cu metal in a given pattern, resulting in excessive metal resistance or a “missing material” defect. Thus, the final process must balance these concerns to achieve a reasonable “process window,” as shown in FIG. 1. FIG. 1 shows the upper metal layer process window as a function of CMP removal rate. In FIG. 1, segment 102 shows the region in which there are shorts due to residual materials resulting from underpolishing. Segment 103 shows the desired process window. Segment 104 shows the region in which there are high resistance lines or metal opens.
Residual barrier or Cu (or other) metal “extra material” defects cause electrical shorts. Residual barrier metal defects are difficult to detect even using optimized inline inspection. Electrical test structures are an attractive alternative for defect detection. Metal “Comb” or “SnakeComb” structures can be used to detect the presence of electrical shorts. FIG. 2 shows a typical metal SnakeComb structure 200, including a snake portion 202, and two comb portions 203, 204. If an extra material defect occurs between the two halves of the comb 203, 204, the resulting electrical short results in excessive leakage current detected during subsequent electrical test. If a missing material defect occurs within the Snake portion 202 of the structure 200, subsequent electrical test shows an open circuit between the two ends of the snake.
Layout patterns on underlying layers can be used to stimulate topography-related failures in metal Combs and SnakeCombs 300 including metal 2 lines 302 and 303, as shown in FIGS. 3A and 3B. FIGS. 3A and 3B show residual metal 2 (M2) 305 shorting lines 302 of a snakecomb structure 300 as a result of dishing in the metal 1 (M1) line (lower layer) 301. The residual M2 metal 305 is in the M1 “dish”. The deposited oxide profile 307 and final polished oxide profile 309 are shown. The residual M2 metal 305 lies beneath the final polished oxide profile 309 (because of the M1 dishing) and is not removed by the polishing. However, the design of the underlying patterns 301 must be carefully constructed in order to stimulate the desired failure modes in a manner which uniquely identifies them from other possible failure modes. Furthermore, the effect of the underlying patterns 301 on the yield of the metal SnakeComb 300 is dependent on the design of the SnakeComb itself. Finally, the test structure should be representative of layout patterns typically used in product chips. This ensures that the results from analysis of the test structure will be relevant to product yield. Modern design flows can result in a huge variation of possible product layout patterns. In view of all of these factors combined, a rigorous design-of-experiments (DOE) for test structures for Cu (or other metal) topography analysis are desired for product yield improvement.